Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores.

Ling Zhuo Gerald R. Morris Viktor K. Prasanna

Published in: IPDPS (2005)

Keyphrases

floating point
fixed point
square root
sparse matrices
fast fourier transform
power reduction
floating point arithmetic
general purpose
hardware implementation
application specific
instruction set
similarity measure
bayesian networks
dynamical systems
memory efficient