Francisco Aznar

Publication Activity (10 Years)

Years Active: 2008-2022
Publications (10 Years): 9

Top Topics

Frequency Response

Interpolation Filter

Top Venues

Int. J. Circuit Theory Appl.

Microelectron. J.

Publications

Antonio D. Martínez-Pérez, Francisco Aznar, Denis Flandre, Santiago Celma
Design-Window Methodology for Inductorless Noise-Cancelling CMOS LNAs. IEEE Access 10 (2022)
Jorge Marqués-García, Alberto Arcusa-Puente, Antonio D. Martínez-Pérez, Francisco Aznar
Modeling frequency response of gm-boosted inductorless Common-Gate LNA. VLSI-SoC (2022)
Antonio D. Martínez-Pérez, Pedro A. Martínez Martínez, Francisco Aznar, Guillermo Royo, Santiago Celma
A Strategy to Achieve Competitive Performance in Basic RF LNAs. LASCAS (2021)
Antonio D. Martínez-Pérez, Pedro A. Martínez Martínez, Guillermo Royo, Francisco Aznar, Santiago Celma
A New Approach to the Design of CMOS Inductorless Common-gate Low-noise Amplifiers. ECCTD (2020)
Antonio D. Martínez-Pérez, Cecilia Gimeno, Denis Flandre, Francisco Aznar, Guillermo Royo, Carlos Sánchez-Azqueta
Methodology for Performance Optimization in Noise- and Distortion-Canceling LNA. SMACD (2019)
Antonio D. Martínez-Pérez, Francisco Aznar, Guillermo Royo, Carlos Sánchez-Azqueta, Santiago Celma
Analysis of mismatch impact on image rejection ratio for passive polyphase filters. Int. J. Circuit Theory Appl. 46 (10) (2018)
Antonio D. Martínez-Pérez, Francisco Aznar, Guillermo Royo, Carlos Sánchez-Azqueta, Santiago Celma
Analysis of the Influence of Component Mismatch on Integrated Passive Polyphase Filters. ISCAS (2018)
Antonio D. Martínez-Pérez, J. Morte, Francisco Aznar, Carlos Sánchez-Azqueta, Santiago Celma
Impact of non-idealities on passive polyphase filter performance. ECCTD (2017)
Carlos Sánchez-Azqueta, Javier Aguirre, Guillermo Royo, Francisco Aznar, Erick Guerrero, Santiago Celma
Design of a low-power quadrature LC-VCO in 65 nm CMOS. ECCTD (2017)
Cecilia Gimeno, Concepción Aldea, Francisco Aznar, Carlos Sánchez-Azqueta, Santiago Celma
1-V continuous-time equalizers for multi-gigabit short-haul optical fiber communications. Int. J. Circuit Theory Appl. 42 (2) (2014)
Cecilia Gimeno, Concepción Aldea, Santiago Celma, Francisco Aznar
Low-voltage low-power CMOS receiver front-end for gigabit short-reach optical communications. Int. J. Circuit Theory Appl. 41 (11) (2013)
Cecilia Gimeno, Concepción Aldea, Santiago Celma, Francisco Aznar
Multi-gigabit analog equalizers for plastic opticalfibers. Microelectron. J. 44 (10) (2013)
Cecilia Gimeno, Concepción Aldea, Santiago Celma, Francisco Aznar, Cristina Azcona
A 1-V CMOS receiver front-end for high-speed SI-POF links. ISCAS (2012)
Cecilia Gimeno, Concepción Aldea, Santiago Celma, Francisco Aznar, Carlos Sánchez-Azqueta
A CMOS continuous-time equalizer for short-reach optical communications. ECCTD (2011)
Francisco Aznar, Santiago Celma, Belén Calvo
A 0.18 μm CMOS linear-in-dB AGC post-amplifier for optical communications. Microelectron. Reliab. 51 (5) (2011)
Carlos Sánchez-Azqueta, Santiago Celma, Francisco Aznar
A 0.18 μm CMOS ring VCO for clock and data recovery applications. Microelectron. Reliab. 51 (12) (2011)
Carlos Sánchez-Azqueta, Santiago Celma, Francisco Aznar
A 3.125 GHz four stage voltage controlled ring oscillator in 0.18 CMOS. ISCAS (2011)
Francisco Aznar, Wolfgang Gaberl, Horst Zimmermann
A 0.18 μm CMOS transimpedance amplifier with 26 dB dynamic range at 2.5 Gb/s. Microelectron. J. 42 (10) (2011)
Francisco Aznar, Santiago Celma, Belén Calvo
A 0.18-µm CMOS 1.25-Gbps front-end receiver for low-cost short reach optical communications. ESSCIRC (2010)
Francisco Aznar, Wolfgang Gaberl, Horst Zimmermann
A Highly Sensitive 2.5 Gb/s Transimpedance Amplifier in CMOS Technology. ISCAS (2009)
Jose Maria Garcia del Pozo, Santiago Celma, Aránzazu Otín, Francisco Aznar
10GBase-LX4 Limiting Amplifier in 0.18 µm CMOS Digital Process with Tunable Shunt-peaking. ISCAS (2009)
Belén Calvo, Santiago Celma, Maria Teresa Sanz, Juan Pablo Alegre, Francisco Aznar
Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2008)