Eugene Shragowitz

Publication Activity (10 Years)

Years Active: 1985-2006
Publications (10 Years): 0

Publications

Sungjae Kim, Eugene Shragowitz
Iterative-Constructive Standard Cell Placer for High Speed and Low Power. ICCD (2006)
Eugene Shragowitz, Habib Youssef, Bing Lu
Iterative Converging Algorithms for Computing Bounds on Durations of Activities in Pert and Pert-Like Models. J. Comb. Optim. 7 (1) (2003)
Jian Liu, Eugene Shragowitz
Transaction-based waveform analysis for IP selection. ASP-DAC (2003)
Jian Liu, Ying Zhao, Eugene Shragowitz, George Karypis
A polynomial time approximation scheme for rectilinear Steiner minimum tree construction in the presence of obstacles. ICECS (2002)
H. Chang, Eugene Shragowitz, Jian Liu, Habib Youssef, Bing Lu, Suphachai Sutanthavibul
Net criticality revisited: an effective method to improve timing in physical design. ISPD (2002)
Jian Liu, Eugene Shragowitz, Wei-Tek Tsai
Combining Hierarchical Filtering, Fuzzy Logic, and Simulation with Software Agents for IP (Intellectual Property) Selection in Electronic Design. Int. J. Artif. Intell. Tools 10 (3) (2001)
Bing Lu, Jun Gu, Xiao-Dong Hu, Eugene Shragowitz
Wire segmenting for buffer insertion based on RSTP-MSP. Theor. Comput. Sci. 262 (1) (2001)
Eugene Shragowitz, Jun-Yong Lee, Eric Q. Kang
Application of fuzzy logic in computer-aided VLSI design. IEEE Trans. Fuzzy Syst. 6 (1) (1998)
Jun-Yong Lee, Eugene Shragowitz
Performance Driven Technology Mapper for FPGAs with Complex Logic Block Structures. ISCAS (1995)
Eric Q. Kang, Eugene Shragowitz
Generic fuzzy logic CAD development tool. ASP-DAC (1995)
Jung-Yong Lee, Eugene Shragowitz
Technology mapping for FPGAs with complex block architectures by fuzzy logic techniques. ASP-DAC (1995)
Eric Q. Kang, Rung-Bin Lin, Eugene Shragowitz
Fuzzy logic approach to VLSI placement. IEEE Trans. Very Large Scale Integr. Syst. 2 (4) (1994)
Suphachai Sutanthavibul, Eugene Shragowitz, Rung-Bin Lin
An adaptive timing-driven placement for high performance VLSIs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (10) (1993)
Jaebum Lee, Eugene Shragowitz, David J. Poli
Bounds on net lengths for high-speed PCB. ICCAD (1993)
Rung-Bin Lin, Eugene Shragowitz
Fuzzy Logic Approach to Placement Problem. DAC (1992)
Habib Youssef, Eugene Shragowitz, Suphachai Sutanthavibul
Prelayout timing analysis of cell-based VLSI designs. Comput. Aided Des. 24 (7) (1992)
Suphachai Sutanthavibul, Eugene Shragowitz
Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement. DAC (1991)
Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen
An analytical approach to floorplan design and optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (6) (1991)
Habib Youssef, Rung-Bin Lin, Eugene Shragowitz
Bounds on Net Delays for Physical Design of Fast Circuits. VLSI (1991)
Suphachai Sutanthavibul, Eugene Shragowitz
An Adaptive Timing-Driven Layout for High Speed VLSI. DAC (1990)
Habib Youssef, Eugene Shragowitz
Timing Constraints for Correct Performance. ICCAD (1990)
Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen
An Analytical Approach to Floorplan Design and Optimization. DAC (1990)
Habib Youssef, Eugene Shragowitz, Lionel Bening
Critical path issue in VLSI design. ICCAD (1989)
Jong Lee, Eugene Shragowitz, Sartaj Sahni
A Hypercube Algorithm for the 0/1 Knapsack Problem. J. Parallel Distributed Comput. 5 (4) (1988)
Jong Lee, Sartaj Sahni, Eugene Shragowitz
A Hypecube Algorithm for the 0/1 Knapsack Problem. ICPP (1987)
Eugene Shragowitz, S. Keel
A global router based on a multicommodity flow model. Integr. 5 (1) (1987)
David E. Krekelberg, Eugene Shragowitz, Gerald E. Sobelman, Li-Shin Lin
Automated layout synthesis in the YASC silicon compiler. DAC (1986)
Surendra Nahar, Sartaj Sahni, Eugene Shragowitz
Simulated annealing and combinatorial optimization. DAC (1986)
Surendra Nahar, Sartaj Sahni, Eugene Shragowitz
Experiments with simulated annealing. DAC (1985)