Surendra Nahar

Publication Activity (10 Years)

Years Active: 1985-1995
Publications (10 Years): 0

Publications

So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
A cell-based hierarchical pitchmatching compaction using minimal LP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (4) (1995)
So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. DAC (1993)
Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo
Time-efficient VLSI artwork analysis algorithms in GOALIE2. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (6) (1989)
Surendra Nahar, Sartaj K. Sahni
Fast algorithm for polygon decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (4) (1988)
Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo
Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2. DAC (1988)
Surendra Nahar, Sartaj Sahni
A time and space efficient net extractor. DAC (1986)
Surendra Nahar, Sartaj Sahni, Eugene Shragowitz
Simulated annealing and combinatorial optimization. DAC (1986)
Surendra Nahar, Sartaj Sahni, Eugene Shragowitz
Experiments with simulated annealing. DAC (1985)