Chi-Yuan Lo

Publication Activity (10 Years)

Years Active: 1982-2011
Publications (10 Years): 0

Publications

Jang-Ping Sheu, Chi-Yuan Lo, Wei-Kai Hu
A Distributed Routing Protocol and Handover Schemes in Hybrid Vehicular Ad Hoc Networks. ICPADS (2011)
Yu-Chee Tseng, Chin-Hao Wu, Fang-Jing Wu, Chi-Fu Huang, Chung-Ta King, Chun-Yu Lin, Jang-Ping Sheu, Chun-Yu Chen, Chi-Yuan Lo, Chien-Wen Yang, Chi-Wen Deng
A Wireless Human Motion Capturing System for Home Rehabilitation. Mobile Data Management (2009)
William H. Kao, Chi-Yuan Lo, Mark Basel, Raminderpal Singh
Parasitic extraction: current state of the art and future trends. Proc. IEEE 89 (5) (2001)
William H. Kao, Chi-Yuan Lo, Raminderpal Singh, Mark Basel
Parasitic extraction: current state of the art and future trends. ISCAS (5) (2001)
So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
A cell-based hierarchical pitchmatching compaction using minimal LP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (4) (1995)
Anoop Singhal, Chi-Yuan Lo
Object oriented data modeling for VLSI/CAD. VLSI Design (1995)
Chi-Yuan Lo, Jirí Matousek, William L. Steiger
Algorithms for Ham-Sandwich Cuts. Discret. Comput. Geom. 11 (1994)
Shun-Lin Su, Charles H. Barry, Chi-Yuan Lo
A space-efficient short-finding algorithm [VLSI layouts]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (8) (1994)
So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. DAC (1993)
Nishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu
HS: a hierarchical search package for CAD data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (1) (1993)
Anoop Singhal, Robert M. Arlein, Chi-Yuan Lo
DDB: An Object Oriented Design Data Manager for VLSI CAD. SIGMOD Conference (1993)
Charles R. Bonapace, Chi-Yuan Lo
An O(n log m) algorithm for VLSI design rule checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (6) (1992)
Chi-Yuan Lo, Jirí Matousek, William L. Steiger
Ham-Sandwich Cuts in R^d STOC (1992)
Debaprosad Dutt, Chi-Yuan Lo
On Minimal Closure Constraint Generation for Symbolic Cell Assembly. DAC (1991)
Nishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu
HS: A Hierarchical Search Package for CAD Data. ICCAD (1990)
Chi-Yuan Lo, Ravi Varadarajan
) 1-d Compaction Algorithm. DAC (1990)
Hyunchul Shin, Chi-Yuan Lo
An Efficient Two-Dimensional Layout Compaction Algorithm. DAC (1989)
Chong-Leong Ong, Jeong-Tyng Li, Chi-Yuan Lo
GENAC: An Automatic Cell Synthesis Tool. DAC (1989)
Anoop Singhal, Nishit P. Parikh, Debaprosad Dutt, Chi-Yuan Lo
A data model and architecture for VLSI/CAD databases. ICCAD (1989)
Charles R. Bonapace, Chi-Yuan Lo
An O(nlogm) Algorithm for VLSI Design Rule Checking. DAC (1989)
Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo
Time-efficient VLSI artwork analysis algorithms in GOALIE2. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (6) (1989)
Chi-Yuan Lo
Automatic Tub Region Generation for Symbolic Layout Compaction. DAC (1989)
Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo
Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2. DAC (1988)
Chi-Yuan Lo, Hao N. Nham, Ajoy K. Bose
Algorithms for an Advanced Fault Simulation System in MOTIS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (2) (1987)
Chin-Fu Chen, Chi-Yuan Lo, Hao N. Nham, Prasad Subramaniam
The second generation motis mixed-mode simulator. DAC (1984)
Chi-Yuan Lo, Hao N. Nham, Ajoy K. Bose
A data structure for MOS circuits. DAC (1983)
Ajoy K. Bose, Patrick Kozak, Chi-Yuan Lo, Hao N. Nham, Ernesto Pacas-Skewes, Kwok W. Wu
A fault simulator for MOS LSI circuits. DAC (1982)