Cho W. Moon

Publication Activity (10 Years)

Years Active: 1991-2002
Publications (10 Years): 0

Publications

Cho W. Moon, Harish Kriplani, Krishna P. Belkhale
Timing model extraction of hierarchical blocks by graph reduction. DAC (2002)
Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
An efficient heuristic procedure for solving the state assignment problem for event-based specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (1) (1995)
Cho W. Moon, Paul R. Stephan, Robert K. Brayton
Specification, synthesis, and verification of hazard-free asynchronous circuits. J. VLSI Signal Process. 7 (1-2) (1994)
Cho W. Moon, Robert K. Brayton
Elimination of Dynamic hazards by Factoring. DAC (1993)
Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Solving the State Assignment Problem for Signal Transition Graphs. DAC (1992)
Ellen Sentovich, Kanwar Jit Singh, Cho W. Moon, Hamid Savoj, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Sequential Circuit Design Using Synthesis and Optimization. ICCD (1992)
Cho W. Moon, Paul R. Stephan, Robert K. Brayton
Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. ICCAD (1991)