Carroll Speir

Publication Activity (10 Years)

Years Active: 2004-2018
Publications (10 Years): 3

Top Topics

Cmos Technology

Hand Eye Coordination

Power Dissipation

Sampling Strategy

Top Venues

IEEE J. Solid State Circuits

Publications

Nevena Rakuljic, Carroll Speir, Eric Otte, Jeff Bray, Corey Petersen, Gabriele Manganaro
In-situ nonlinear calibration of a RF signal chain. ISCAS (2018)
Siddharth Devarajan, Larry Singer, Dan Kelly, Steve Kosic, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow
16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology. ISSCC (2017)
Siddharth Devarajan, Larry Singer, Dan Kelly, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow, Gabriele Manganaro
A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology. IEEE J. Solid State Circuits 52 (12) (2017)
Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Russell Stop
A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration. IEEE J. Solid State Circuits 49 (12) (2014)
Ahmed M. Abdelatty Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, David Jarman, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Ho-Young Lee
29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration. ISSCC (2014)
Ahmed M. A. Ali, Andy Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Mike Hensley, Russell Stop, Paritosh Bhoraskar, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed
A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration. ISSCC (2010)
Ahmed M. A. Ali, Andrew S. Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Paritosh Bhoraskar, Hüseyin Dinc, Mike Hensley, Russell Stop, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed
A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration. IEEE J. Solid State Circuits 45 (12) (2010)
Mike Hensley, Carroll Speir, Russell Stop, Kevin Behel, Carl Moreland, Greg Patterson, Dan Kelly, Manish Manglani, Michael Elliott, Scott Puckett, Joe Young, Frank Murden
A dual channel IF-digitizing IC with 117dB dynamic range at 300Mhz IF for EDGE/GSM base-stations [receiver]. CICC (2004)