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Carlos Ornelas
Publication Activity (10 Years)
Years Active: 2012-2013
Publications (10 Years): 0
Top Topics
Nm Technology
Integrated Circuit
Power Management
Sampling Procedure
Top Venues
ISSCC
ESSCIRC
IEEE J. Solid State Circuits
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Publications
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Hyung Seok Kim
,
Carlos Ornelas
,
Kailash Chandrashekar
,
Dan Shi
,
Pin-en Su
,
Paolo Madoglio
,
Yee William Li
,
Ashoke Ravi
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique.
IEEE J. Solid State Circuits
48 (7) (2013)
Hyung Seok Kim
,
Carlos Ornelas
,
Kailash Chandrashekar
,
Pin-en Su
,
Paolo Madoglio
,
Yee William Li
,
Ashoke Ravi
6-bit PVT and mismatch insensitive TDC.
ESSCIRC
(2012)
Y. William Li
,
Carlos Ornelas
,
Hyung Seok Kim
,
Hasnain Lakdawala
,
Ashoke Ravi
,
Krishnamurthy Soumyanath
A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS.
ISSCC
(2012)