ByongChan Lim

Publication Activity (10 Years)

Years Active: 2009-2020
Publications (10 Years): 7

Top Topics

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Sung-Jin Kim, Zachary Myers, Steven Herbst, ByongChan Lim, Mark Horowitz
Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator. CoRR (2020)
Sung-Jin Kim, Zachary Myers, Steven Herbst, ByongChan Lim, Mark Horowitz
Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator. VLSI Circuits (2020)
Steven Herbst, ByongChan Lim, Mark Horowitz
Fast FPGA emulation of analog dynamics in digitally-driven systems. CoRR (2020)
ByongChan Lim, Mark Horowitz
An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Steven Herbst, ByongChan Lim, Mark Horowitz
Fast FPGA emulation of analog dynamics in digitally-driven systems. ICCAD (2018)
ByongChan Lim, Mark Horowitz
Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2016)
Suyao Ji, Jing Pu, ByongChan Lim, Mark Horowitz
A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture. VLSI Circuits (2016)
ByongChan Lim, Ji-Eun Jang, James Mao, Jaeha Kim, Mark Horowitz
Digital Analog Design: Enabling Mixed-Signal System Validation. IEEE Des. Test 32 (1) (2015)
Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao
Fortifying analog models with equivalence checking and coverage analysis. DAC (2010)
ByongChan Lim, Jaeha Kim, Mark A. Horowitz
An efficient test vector generation for checking analog/mixed-signal functional models. DAC (2010)
Jaeha Kim, Metha Jeeradit, ByongChan Lim, Mark A. Horowitz
Leveraging designer's intent: A path toward simpler analog CAD tools. CICC (2009)