Ji-Eun Jang

Publication Activity (10 Years)

Years Active: 2009-2015
Publications (10 Years): 0

Top Topics

Agent Based Modeling

Markup Language

Information Delivery

Simulation Models

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

ByongChan Lim, Ji-Eun Jang, James Mao, Jaeha Kim, Mark Horowitz
Digital Analog Design: Enabling Mixed-Signal System Validation. IEEE Des. Test 32 (1) (2015)
Ji-Eun Jang, Jaeha Kim
PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Jaeha Kim, Si-Jung Yang, Ji-Eun Jang
PPV-based modeling and event-driven simulation of injection-locked oscillators in SystemVerilog. CICC (2014)
Ji-Eun Jang, Si-Jung Yang, Jaeha Kim
Event-driven simulation of Volterra series models in SystemVerilog. CICC (2013)
Ji-Eun Jang, Myeong-Jae Park, Jaeha Kim
An event-driven simulation methodology for integrated switching power supplies in SystemVerilog. DAC (2013)
Ji-Eun Jang, Myeong-Jae Park, Dongyun Lee, Jaeha Kim
True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example. CICC (2012)
Ji-Eun Jang
Comparator-based switched-capacitor pipelined ADC with background offset calibration. ISCAS (2011)
Kuan-Yu Lin, Ji-Eun Jang, Ching-Hsuan Hsieh, Yung-Pin Lee
A pipelined analog-to-digital converter using incomplete-settling-without-slewing technique. ISCAS (2010)
Ji-Eun Jang, Yung-Kuang Miao, Yung-Pin Lee
High-bandwidth power-scalable 10-bit pipelined ADC using bandwidth-reconfigurable operational amplifier. ISCAS (2010)
Dong Hun Shin, Ji-Eun Jang, Frank O'Mahony, C. Patrick Yue
A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS. CICC (2009)