Bahram Rashidi

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 32

Top Topics

Low Time Complexity

Top Venues

Microelectron. J.

Int. J. Circuit Theory Appl.

IET Comput. Digit. Tech.

IET Circuits Devices Syst.

Publications

Bahram Rashidi
Efficient and low-cost approximate multipliers for image processing applications. Integr. 94 (2024)
Bahram Rashidi
APPAs: fast and efficient approximate parallel prefix adders and multipliers. J. Supercomput. 80 (16) (2024)
Bahram Rashidi
Fault-tolerant and error-correcting 4-bit S-boxes for cryptography applications with multiple errors detection. J. Supercomput. 80 (2) (2024)
Bahram Rashidi
Error-correcting cryptographic S-boxes with multiple error detection and correction. Int. J. Circuit Theory Appl. 51 (11) (2023)
Bahram Rashidi
Lightweight Cryptographic S-Boxes Based on Efficient Hardware Structures for Block Ciphers. ISC Int. J. Inf. Secur. 15 (1) (2023)
Bahram Rashidi
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter. Integr. 85 (2022)
Bahram Rashidi
Compact and efficient structure of 8-bit S-box for lightweight cryptography. Integr. 76 (2021)
Bahram Rashidi
Flexible and high-throughput structures of Camellia block cipher for security of the Internet of Things. IET Comput. Digit. Tech. 15 (3) (2021)
Bahram Rashidi
Efficient full data-path width and serialized hardware structures of SPONGENT lightweight hash function. Microelectron. J. 115 (2021)
Bahram Rashidi
Lightweight 8-bit S-box and combined S-box/S-box-1 for cryptographic applications. Int. J. Circuit Theory Appl. 49 (8) (2021)
Bahram Rashidi
Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication. J. Hardw. Syst. Secur. 4 (2) (2020)
Bahram Rashidi
Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher. IET Comput. Digit. Tech. 14 (2) (2020)
Bahram Rashidi
Flexible structures of lightweight block ciphers PRESENT, SIMON and LED. IET Circuits Devices Syst. 14 (3) (2020)
Bahram Rashidi
Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher. Int. J. Circuit Theory Appl. 48 (8) (2020)
Bahram Rashidi, Mohammad Abedini
Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems. J. Circuits Syst. Comput. 28 (9) (2019)
Bahram Rashidi
Efficient and high-throughput application-specific integrated circuit implementations of HIGHT and PRESENT block ciphers. IET Circuits Devices Syst. 13 (6) (2019)
Bahram Rashidi
High-throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers. Int. J. Circuit Theory Appl. 47 (8) (2019)
Bahram Rashidi
Efficient hardware structure for extended Euclidean-based inversion over F 2 m. IET Comput. Digit. Tech. 13 (4) (2019)
Bahram Rashidi
High-throughput and lightweight hardware structures of HIGHT and PRESENT block ciphers. Microelectron. J. 90 (2019)
Bahram Rashidi
Efficient hardware implementations of point multiplication for binary Edwards curves. Int. J. Circuit Theory Appl. 46 (8) (2018)
Bahram Rashidi
A Survey on Hardware Implementations of Elliptic Curve Cryptosystems. CoRR (2017)
Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
) for elliptic curve cryptosystems. IET Circuits Devices Syst. 11 (2) (2017)
Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi
). IET Inf. Secur. 11 (2) (2017)
Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi
High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves. IACR Cryptol. ePrint Arch. 2017 (2017)
Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
Full-custom hardware implementation of point multiplication on binary Edwards curves for application-specific integrated circuit elliptic curve cryptosystem applications. IET Circuits Devices Syst. 11 (6) (2017)
Bahram Rashidi
. Microelectron. J. 63 (2017)
Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
). Integr. 55 (2016)
Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
). IET Comput. Digit. Tech. 10 (1) (2016)
Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m). IACR Cryptol. ePrint Arch. 2016 (2016)
Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems. Microelectron. J. 52 (2016)
Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
Efficient and Low-complexity Hardware Architecture of Gaussian Normal Basis Multiplication over GF(2m) for Elliptic Curve Cryptosystems. IACR Cryptol. ePrint Arch. 2015 (2015)
Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi
Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields. ISC Int. J. Inf. Secur. 7 (2) (2015)
Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi
) for elliptic curve cryptosystems. ISCISC (2014)
Reza Rezaeian Farashahi, Bahram Rashidi, Sayed Masoud Sayedi
FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm. Microelectron. J. 45 (8) (2014)
Bahram Rashidi
High performance and low-power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA. IET Signal Process. 7 (8) (2013)