Bahniman Ghosh

Publication Activity (10 Years)

Years Active: 2013-2015
Publications (10 Years): 0

Top Topics

Silicon On Insulator

Schottky Barrier

Cellular Automata

Top Venues

J. Low Power Electron.

Int. J. Circuit Theory Appl.

J. Circuits Syst. Comput.

Publications

Puneet Agrawal, Bahniman Ghosh
Innovative design methodologies in quantum-dot cellular automata. Int. J. Circuit Theory Appl. 43 (2) (2015)
Bahniman Ghosh, Punyasloka Bal, Partha Mondal, M. W. Akram
by Drain Engineering and Work Function Engineering. J. Low Power Electron. 10 (1) (2014)
Bahniman Ghosh, Neelam Surana, M. W. Akram, Ball Mukund Mani Tripathi
As Channel Double Gate Junctionless Transistor. J. Low Power Electron. 10 (1) (2014)
Shibir Basak, Bahniman Ghosh
Effect of Traps on the Performance of Nanowire Si Junctionless Tunnel FET. J. Low Power Electron. 10 (4) (2014)
Bahniman Ghosh, Partha Mondal, M. W. Akram, Punyasloka Bal
Impact of High- Spacer on Junctionless Transistor in Sub-Threshold Regime. J. Low Power Electron. 10 (2) (2014)
Bahniman Ghosh, A. Ajay
2-Bit Full Adder Implementation Using Single Spin Logic Paradigm. J. Low Power Electron. 10 (2) (2014)
Bahniman Ghosh, Jangam Siva Chandra, Akshay Kumar Salimath
Design of a Multi-Layered QCA Configurable Logic Block for FPGAs. J. Circuits Syst. Comput. 23 (6) (2014)
Himanshu Gupta, Bahniman Ghosh
Transistor size optimization in digital circuits using ant colony optimization for continuous domain. Int. J. Circuit Theory Appl. 42 (6) (2014)
Ankit Kumar Verma, Bahniman Ghosh, Bhaskar Awadhiya, Tangudu Bharat Kumar
Modeling of Effect of Boron and Phosphorus Doping in CoFe/MgO Magnetic Tunnel Junctions. J. Low Power Electron. 10 (3) (2014)
Bahniman Ghosh, Aayush Gupta
Spin Transport in Single Layer Germanene: The Role of Electron Electron Scattering. J. Low Power Electron. 10 (3) (2014)
Jangam Siva Chandra, Kandula Suresh, Bahniman Ghosh
Clocking Scheme Implementation for Multi-Layered Quantum Dot Cellular Automata Design. J. Low Power Electron. 10 (2) (2014)
Arun Kant Sharma, Shiva Asapu, Akshay Kumar Salimath, Bahniman Ghosh
Read and Write Analysis for Balanced Pattern Memristor Crossbar Array. J. Low Power Electron. 10 (1) (2014)
Bahniman Ghosh, Shibir Basak, Pranav Kumar Asthana
Performance Improvement in Nanoscale Ge-GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate. J. Low Power Electron. 10 (3) (2014)
M. W. Akram, Bahniman Ghosh
Junctionless Silicon-Nanowire Gate-All-Around Tunnel Field Effect Transistor. J. Low Power Electron. 10 (2) (2014)
Tangudu Bharat Kumar, Bhaskar Awadhiya, E. MeherAbhinav, Bahniman Ghosh, Bhupesh Bishnoi
Performance Analysis of Spin Transfer Torque Random Access Memory with cross shaped free layer using Heusler Alloys by using micromagnetic studies. CoRR (2014)
Yuvaneet Bhaker, Princepreet Singh, Bahniman Ghosh
Simulation of 2 Bit by 2 Bit Binary Multiplier Using Magnetic Tunnel Junction Device. J. Low Power Electron. 10 (4) (2014)
Bahniman Ghosh, Abhinay Kumar
Quantum-Dot Cellular Automata-Implementing Reversible Benchmarks. J. Low Power Electron. 10 (3) (2014)
Bahniman Ghosh, Gaurav S. Solanki, Abhishek B. Banerjee
Domain Wall Dynamics Due to Voltage Controlled Magnetic Anisotropy. J. Low Power Electron. 10 (1) (2014)
Bahniman Ghosh, Aayush Gupta
Effect of Nanoribbon Width and Strain on the Electronic Properties of the WS2 Nanoribbon. J. Low Power Electron. 10 (3) (2014)
Bahniman Ghosh, Uzma Khan, Ball Mukund Mani Tripathi, M. W. Akram
Ultrathin Compound Semiconductor in Bulk Planar Junctionless Transistor for High-Performance Nanoscale Transistors. J. Low Power Electron. 9 (4) (2013)
Yogesh Goswami, Ball Mukund Mani Tripathi, Pranav Kumar Asthana, Bahniman Ghosh
Junctionless Tunnel Field Effect Transistor with Enhanced Performance Using III-V Semiconductor. J. Low Power Electron. 9 (4) (2013)
Uzma Khan, Bahniman Ghosh, M. W. Akram
Effect of Self Heating on Selective Buried Oxide and Silicon on Insulator Based Junctionless Transistors. J. Low Power Electron. 9 (3) (2013)
Bahniman Ghosh, Chandramauli Singh, Akshay Kumar Salimath
A Novel Approach of Full Adder and Arithmetic Logic Unit Design in Quantum Dot Cellular Automata. J. Low Power Electron. 9 (4) (2013)