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A. N. Nagamani
ORCID
Publication Activity (10 Years)
Years Active: 2011-2019
Publications (10 Years): 6
Top Topics
Engineering Design
Verilog Hdl
Future Trends
Markov Chain
Top Venues
ICICS
EEET
RAIT
J. Electron. Test.
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Publications
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S. S. Rekha
,
A. N. Nagamani
Hardware Security-present and Future Trends.
EEET
(2019)
A. N. Nagamani
,
S. N. Anuktha
,
N. Nanditha
,
Vinod Kumar Agrawal
A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
37 (2) (2018)
A. N. Nagamani
,
Chirag Ramesh
,
Vinod Kumar Agrawal
Design of Optimized Reversible Squaring and Sum-of-Squares Units.
Circuits Syst. Signal Process.
37 (4) (2018)
A. N. Nagamani
,
Vijetha Ravichander
,
Madhumita Harish
,
Vinod Kumar Agrawal
DFT methodologies for testing k-CNOT, Fredkin and Peres based reversible circuits.
RAIT
(2018)
A. N. Nagamani
,
S. Ashwin
,
B. Abhishek
,
Vinod Kumar Agrawal
An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits.
J. Electron. Test.
32 (2) (2016)
A. N. Nagamani
,
S. Ashwin
,
B. Abhishek
,
K. V. Arjun
,
Vinod Kumar Agrawal
Design and Analysis of Multiple Parameters Optimized n-Bit Reversible Magnitude Comparators.
J. Circuits Syst. Comput.
25 (9) (2016)
A. N. Nagamani
,
H. Vishnu Prasad
,
Rajendra S. Hathwar
,
Vinod Kumar Agrawal
Design of optimized reversible multiplier for high speed DSP application.
ICICS
(2015)
Himanshu Thapliyal
,
H. V. Jayashree
,
A. N. Nagamani
,
Hamid R. Arabnia
Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder.
Trans. Comput. Sci.
17 (2013)
A. N. Nagamani
,
S. Nishchai
Quaternary High Performance Arithmetic Logic Unit Design.
DSD
(2011)