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Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM.
Taehui Na
Jung Pill Kim
Seung-Hyuk Kang
Seong-Ook Jung
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2016)
Keyphrases
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random access memory
power reduction
high speed
real time
delay insensitive
sensor networks
design considerations
tunnel diode
data acquisition
primal dual
reduction method
circuit design
analog circuits
learning stage