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Soft-Error Susceptibility in Flip-Flop in EUV 7 nm Bulk-FinFET Technology.

Taiki UemuraByungjin ChungJeongmin JoMijoung KimDalhee LeeGunrae KimSeungbae LeeTaesjoong SongHwasung RheeBrandon LeeJaehee Choi
Published in: IRPS (2021)
Keyphrases
  • cmos technology
  • case study
  • power consumption
  • real time
  • power dissipation
  • flip flops
  • computer systems
  • error rate
  • nm technology