• search
    search
  • reviewers
    reviewers
  • feeds
    feeds
  • assignments
    assignments
  • settings
  • logout

Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.

Mihalis PsarakisDimitris GizopoulosAntonis M. PaschalisYervant Zorian
Published in: IEEE Trans. Computers (2000)
Keyphrases
  • delay insensitive
  • low cost
  • neural network
  • focal plane
  • fault detection
  • real time
  • artificial intelligence
  • image processing
  • hidden markov models
  • high speed
  • infrared
  • automated reasoning
  • image sensor
  • digital circuits