An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology.

Qingyu Chen Haibin Wang Li Chen Lixiang Li Xing Zhao Rui Liu Mo Chen Xuantian Li

Published in: J. Electron. Test. (2016)

Keyphrases

cmos technology
low power
power consumption
low voltage
spl times
parallel processing
high speed
low cost
power dissipation
silicon on insulator
image sensor
mixed signal
leakage current
embedded dram
pattern recognition
power management
hardware implementation
digital images
random access memory
moving objects