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SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology.

Clement ChampeixNicolas BorrelJean-Max DutertreBruno RobissonMathieu LisartAlexandre Sarafianos
Published in: DFTS (2015)
Keyphrases
  • cmos technology
  • low power
  • flip flops
  • power consumption
  • power dissipation
  • spl times
  • parallel processing
  • low voltage
  • low cost
  • high speed
  • image sensor
  • silicon on insulator
  • pattern matching