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Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power.

Behzad ZeinaliJens Kargaard MadsenPraveen RaghavanFarshad Moradi
Published in: ISVLSI (2015)
Keyphrases
  • power consumption
  • cmos technology
  • case study
  • nm technology
  • power dissipation
  • cost effective
  • power reduction
  • design process
  • access control
  • computer systems
  • current status
  • chip design