A Novel Solution for Chip-Level Functional Timing Verification.

Rathish Jayabharathi Kyung Tek Lee Jacob A. Abraham

Published in: VTS (1997)

Keyphrases

functional verification
optimal solution
high speed
low cost
neural network
image processing
case study
levels of abstraction
real time
petri net
mathematical model
integer programming
exact solution
linear equations
signature verification
vlsi design