A New Low Power Test Pattern Generator for BIST Architecture.
Kicheol KimDongSub SongIncheol KimSungho KangPublished in: IEICE Trans. Electron. (2005)
Keyphrases
- low power
- pattern generator
- vlsi architecture
- power consumption
- low cost
- high speed
- mixed signal
- cmos technology
- single chip
- wireless transmission
- logic circuits
- high power
- low power consumption
- nm technology
- digital signal processing
- real time
- built in self test
- design considerations
- delay insensitive
- vlsi circuits
- signal processor
- gate array
- cmos image sensor
- vlsi implementation
- power dissipation
- image sensor
- general purpose