Partitioned instruction cache architecture for energy efficiency.
Soontae KimNarayanan VijaykrishnanMahmut T. KandemirAnand SivasubramaniamMary Jane IrwinPublished in: ACM Trans. Embed. Comput. Syst. (2003)
Keyphrases
- energy efficiency
- memory hierarchy
- energy consumption
- power consumption
- wireless sensor networks
- power management
- sensor networks
- energy efficient
- data center
- energy management
- response time
- high performance computing
- power saving
- instruction set
- energy saving
- energy aware
- smart home
- routing protocol
- main memory
- traffic load
- real time
- memory access
- sensor nodes
- wireless sensor
- multithreading
- cache misses
- base station
- prefetching
- battery powered
- energy conservation
- data collection
- management system
- query processing