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The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic.

David BolCédric HocquetDenis FlandreJean-Didier Legat
Published in: ESSCIRC (2010)
Keyphrases
  • low voltage
  • random access memory
  • design considerations
  • power line
  • cmos technology
  • high speed
  • delay insensitive
  • real time
  • sensor networks
  • low power
  • asynchronous circuits