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Chip-package hybrid clock distribution network and DLL for low jitter clock delivery.
Daehyun Chung
Chunghyun Ryu
Hyungsoo Kim
Choonheung Lee
Jinhan Kim
Kicheol Bae
Jiheon Yu
Hoi-Jun Yoo
Joungho Kim
Published in:
IEEE J. Solid State Circuits (2006)
Keyphrases
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distribution network
high speed
route optimization
power consumption
distribution systems
decision making
supply chain
traveling salesman problem
packet loss
particle swarm