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Chip-package hybrid clock distribution network and DLL for low jitter clock delivery.

Daehyun ChungChunghyun RyuHyungsoo KimChoonheung LeeJinhan KimKicheol BaeJiheon YuHoi-Jun YooJoungho Kim
Published in: IEEE J. Solid State Circuits (2006)
Keyphrases
  • distribution network
  • high speed
  • route optimization
  • power consumption
  • distribution systems
  • decision making
  • supply chain
  • traveling salesman problem
  • packet loss
  • particle swarm