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Design and early evaluation of a 3-D die stacked chip multi-vector processor.
Ryusuke Egawa
Yusuke Funaya
Ryu-ichi Nagaoka
Akihiro Musa
Hiroyuki Takizawa
Hiroaki Kobayashi
Published in:
3DIC (2010)
Keyphrases
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single chip
high speed
functional verification
circuit design
formative evaluation
chip design
memory subsystem
parallel processing
physical design
low cost
computer systems
low power
design methodology
evaluation model
computer architecture
vlsi implementation