A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS.

Jung-Yu Chang Shen-Iuan Liu

Published in: IET Circuits Devices Syst. (2009)

Keyphrases

leakage current
low voltage
phase locked loop
high speed
cmos technology
power line
design considerations
random access memory
power consumption
high voltage
power management
multipath
low power
electrical properties
response time