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Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators.
Mahdi Taheri
Natalia Cherezova
Mohammad Saeed Ansari
Maksim Jenihhin
Ali Mahani
Masoud Daneshtalab
Jaan Raik
Published in:
ISQED (2024)
Keyphrases
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systolic array
reconfigurable architecture
data flow
fault detection
parallel architecture
fault diagnosis
fault tree
information processing
single chip
pattern recognition
computing systems
computing platform
image processing
scheduling problem
higher order
hardware implementation