A novel five-transistor (5T) sram cell for high performance cache.
Michael WieckowskiMartin MargalaPublished in: SoCC (2005)
Keyphrases
- embedded processors
- low power
- single chip
- embedded dram
- power consumption
- leakage current
- high speed
- random access memory
- memory subsystem
- dynamic random access memory
- metal oxide semiconductor
- integrated circuit
- data transmission
- query processing
- parallel implementation
- prefetching
- low cost
- hit rate
- high efficiency
- back end
- main memory
- caching scheme
- data access
- coarse grained
- microscopy images
- power dissipation
- multithreading
- low voltage
- real time