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Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity.
Bon Woong Ku
Taigon Song
Arthur Nieuwoudt
Sung Kyu Lim
Published in:
ISLPED (2017)
Keyphrases
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high speed
power dissipation
power consumption
low cost
low power
optimization method
high density
optimization problems
global optimization
optimization process
integrated circuit
ibm power processor
higher level
constrained optimization
power management
inter cell