Login / Signup
A D&T Roundtable: Testing Mixed Logic and DRAM Chips.
Meh-Ron Amerian
William D. Atwell Jr.
Ian Burgess
Gary D. Fleeman
David Y. Lepejian
T. W. Williams
Farzad Zarrinfar
Yervant Zorian
Published in:
IEEE Des. Test Comput. (1998)
Keyphrases
</>
high density
chip design
high speed
predicate logic
test cases
main memory
classical logic
integrated circuit
logic programming
automated reasoning
computer systems
data center
modal logic
software testing
defeasible logic
deontic logic
knowledge representation