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Early wire characterization for predictable network-on-chip global interconnects.

Ilhan HatirnazStéphane BadelNuria PazosYusuf LeblebiciSrinivasan MuraliDavid AtienzaGiovanni De Micheli
Published in: SLIP (2007)
Keyphrases
  • network on chip
  • power dissipation
  • routing algorithm
  • cmos technology
  • high speed
  • parallel processing