Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs.
Pruek Vanna-IampikulChengjia ShaoYi-Chen LuSai PentapatiYun HeoJae-Seung ChoiSung Kyu LimPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2023)