Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits.
Alexandru AmaricaiSergiu NimaraOana BoncaloJiaoyan ChenEmanuel M. PopoviciPublished in: DSD (2014)
Keyphrases
- cmos technology
- high speed
- circuit design
- analog vlsi
- low power
- delay insensitive
- vlsi circuits
- probabilistic model
- fault diagnosis
- bayesian networks
- low cost
- uncertain data
- probabilistic modeling
- fault detection
- low voltage
- asynchronous circuits
- power dissipation
- statistical modeling
- probabilistic reasoning
- real time
- modeling language
- higher level
- neural network