A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control.
Luke R. EversonSachin S. SapatnekarChris H. KimPublished in: ISSCC (2019)
Keyphrases
- physical design
- circuit design
- single chip
- control system
- low cost
- graph structure
- nearest neighbor
- graph theory
- graph model
- design methodology
- bipartite graph
- memory requirements
- high speed
- random access memory
- memory subsystem
- graph mining
- hardware implementation
- graph representation
- edge detection
- multithreading
- memory access
- embedded dram