40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode.
Kedar Janardan DhoriPromod KumarChristophe LecocqPascal UrardOlivier CallenFlorian CachoMaryline ParraPrashant PandeyDaniel NobletPublished in: VLSID (2022)