Login / Signup

An efficient linearity test for on-chip high speed ADC and DAC using loop-back.

Ji Hwan (Paul) ChunHak-soo YuJacob A. Abraham
Published in: ACM Great Lakes Symposium on VLSI (2004)
Keyphrases
  • high speed
  • low power
  • single chip
  • high speed networks
  • max csp
  • database
  • real time
  • low cost
  • statistical significance
  • data sets
  • test cases
  • test data
  • analog vlsi