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An efficient linearity test for on-chip high speed ADC and DAC using loop-back.
Ji Hwan (Paul) Chun
Hak-soo Yu
Jacob A. Abraham
Published in:
ACM Great Lakes Symposium on VLSI (2004)
Keyphrases
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high speed
low power
single chip
high speed networks
max csp
database
real time
low cost
statistical significance
data sets
test cases
test data
analog vlsi