A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.
Mohammad H. TehranipourSeid Mehdi FakhraieZainalabedin NavabiM. R. MovahedinPublished in: J. Electron. Test. (2004)
Keyphrases
- dynamic random access memory
- low cost
- embedded dram
- memory subsystem
- random access memory
- processor core
- central processing unit
- real time
- low power
- high speed
- single chip
- level parallelism
- embedded systems
- multi core processors
- instruction set
- memory access
- ibm zenterprise
- ibm power processor
- parallel architecture
- multi processor
- embedded processors
- design considerations
- general purpose processors
- cmos technology
- industry standard
- management system
- parallel processing
- power consumption
- data acquisition
- multi core architecture
- operating system