The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor.

Don Weiss John J. Wuu Victor Chin

Published in: IEEE J. Solid State Circuits (2002)

Keyphrases

memory subsystem
high speed
processor core
circuit design
physical design
low cost
multithreading
functional verification
higher level
ibm zenterprise
high density
data structure
silicon on insulator