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A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches.
Ki Chul Chun
Pulkit Jain
Tae-Ho Kim
Chris H. Kim
Published in:
IEEE J. Solid State Circuits (2012)
Keyphrases
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high speed
embedded dram
cmos technology
low power
random access memory
memory access
power consumption
low voltage
low cost
design considerations
dynamic random access memory
frame rate
database
real time
image sensor
prefetching
memory subsystem
motion estimation