Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement.
Yasuhiro OgasaharaTakashi EnamiMasanori HashimotoTakashi SatoTakao OnoyePublished in: IEEE Trans. Circuits Syst. II Express Briefs (2007)
Keyphrases
- simulation model
- power dissipation
- phase locked loop
- low cost
- high speed
- simulation models
- agent based simulation
- high density
- discrete event
- analog vlsi
- simulation environment
- single chip
- mathematical model
- simulation tool
- matlab simulink
- high voltage
- analytical model
- power consumption
- end to end delay
- cmos technology
- power system