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Takashi Enami
Publication Activity (10 Years)
Years Active: 2006-2015
Publications (10 Years): 0
Top Topics
Noise Model
Vlsi Architecture
Fuzzy Pid Control
Power Distribution
Top Venues
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
WiSNet
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Publications
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Takashi Enami
,
Kentaro Kawakami
,
Hiroshi Yamazaki
DMA-driven control method for low power sensor node.
WiSNet
(2015)
Takashi Enami
,
Takashi Sato
,
Masanori Hashimoto
Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2012)
Takashi Enami
,
Shinyu Ninomiya
,
Kenichi Shinkai
,
Shinya Abe
,
Masanori Hashimoto
Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2010)
Takashi Enami
,
Shinyu Ninomiya
,
Masanori Hashimoto
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
28 (4) (2009)
Takashi Enami
,
Shinyu Ninomiya
,
Masanori Hashimoto
Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise.
ISPD
(2008)
Takashi Enami
,
Masanori Hashimoto
,
Takashi Sato
Decoupling capacitance allocation for timing with statistical noise model and timing analysis.
ICCAD
(2008)
Yasuhiro Ogasahara
,
Takashi Enami
,
Masanori Hashimoto
,
Takashi Sato
,
Takao Onoye
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement.
IEEE Trans. Circuits Syst. II Express Briefs
(10) (2007)
Yasuhiro Ogasahara
,
Takashi Enami
,
Masanori Hashimoto
,
Takashi Sato
,
Takao Onoye
Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation.
CICC
(2006)