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Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits.
Xiangdong Xuan
Abhijit Chatterjee
Adit D. Singh
Published in:
ETS (2004)
Keyphrases
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logic circuits
low power
low cost
power consumption
high speed
functional decomposition
gate array
power dissipation
logic synthesis
ultra low power
tunnel diode
pattern recognition
computer vision
single chip
circuit design
design process
user interface
case study