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Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits.
Rongliang Fu
Zhimin Zhang
Guang-Ming Tang
Junying Huang
Xiaochun Ye
Dongrui Fan
Ninghui Sun
Published in:
ACM Great Lakes Symposium on VLSI (2020)
Keyphrases
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design automation
logic circuits
low power
delay insensitive
power consumption
asynchronous circuits
high speed
image processing
test generation
low cost
real time
computer vision
data model
open source
digital signal processing