A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS.
Ruiqi GuoYonggang LiuShixuan ZhengSsu-Yen WuPeng OuyangWin-San KhwaXi ChenJia-Jing ChenXiudong LiLeibo LiuMeng-Fan ChangShaojun WeiShouyi YinPublished in: VLSI Circuits (2019)
Keyphrases
- speech recognition
- random access memory
- embedded dram
- dynamic random access memory
- low voltage
- design considerations
- hidden markov models
- cmos technology
- power consumption
- language model
- silicon on insulator
- recurrent neural networks
- high speed
- speech processing
- speech recognizer
- nm technology
- low power
- automatic speech recognition
- pattern recognition
- speech synthesis
- metal oxide semiconductor
- memory access
- noisy environments
- speech recognition systems
- speech signal
- speech recognition technology
- neural network
- speaker identification
- bayesian networks
- speaker dependent
- machine learning
- leakage current
- speech retrieval
- memory subsystem
- parallel processing
- speech recognition errors
- isolated word
- memory management
- flash memory
- probabilistic model
- computer vision