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Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks.
Philip Jacob
Aamir Zia
Okan Erdogan
Paul M. Belemjian
Jin Woo Kim
Michael Chu
Russell P. Kraft
John F. McDonald
Kerry Bernstein
Published in:
Proc. IEEE (2009)
Keyphrases
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high speed
memory management
memory size
random access memory
memory usage
memory requirements
memory space
computing power
memory subsystem
level parallelism
neural network
random access
single chip
computational power
multi threaded
low power
power consumption
low cost
general purpose