HLDTL: High-performance, low-cost, and double node upset tolerant latch design.
Aibin YanZhengfeng HuangMaoxiang YiJie CuiHuaguo LiangPublished in: VTS (2017)
Keyphrases
- low cost
- design process
- low power consumption
- single chip
- high reliability
- data sets
- optimal design
- design decisions
- building blocks
- cost effective
- software architecture
- power consumption
- computer aided
- design principles
- user interface
- design methodology
- high density
- search engine
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- information retrieval
- databases
- real time