HLDTL: High-performance, low-cost, and double node upset tolerant latch design.

Aibin Yan Zhengfeng Huang Maoxiang Yi Jie Cui Huaguo Liang

Published in: VTS (2017)

Keyphrases

low cost
design process
low power consumption
single chip
high reliability
data sets

optimal design
design decisions
building blocks
cost effective
software architecture
power consumption

computer aided
design principles
user interface
design methodology
high density

search engine
design space
information retrieval
databases
real time