Fast congestion-aware timing-driven placement for island FPGA.
Jinpeng ZhaoQiang ZhouYici CaiPublished in: DDECS (2009)
Keyphrases
- high speed
- data driven
- hardware implementation
- field programmable gate array
- real time image processing
- low cost
- signal processing
- hardware design
- verilog hdl
- case study
- image processing
- data acquisition
- neural network
- single chip
- parallel architecture
- hardware architecture
- fpga implementation
- digital signal
- parallel hardware
- hopf bifurcation