Towards SRAM leakage power minimization by aggressive standby voltage scaling - Experiments on 40nm test chips.
Xin FanJan StuijtTobias GemmekePublished in: DFT (2017)
Keyphrases
- power consumption
- leakage current
- low voltage
- clock gating
- low power
- power management
- power reduction
- cmos technology
- electrical properties
- power dissipation
- power losses
- power saving
- high speed
- power system
- objective function
- operating conditions
- nm technology
- design considerations
- transmission line
- power line
- data transmission
- electrical power