Scheduling unequal length tests in high performance VLSI system implementations.
John Y. SayahCharles R. KimePublished in: ICCD (1989)
Keyphrases
- scheduling problem
- random number generators
- signal processing
- round robin
- high speed
- scheduling algorithm
- resource allocation
- cost effective
- vlsi design
- dynamic scheduling
- scientific computing
- efficient implementation
- high reliability
- multiple choice
- neural network
- real time database systems
- maximum number
- statistical tests
- parallel machines
- test data
- total length
- vlsi circuits
- processor array
- database