Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs.

Kan Xu Ravi Patel Praveen Raghavan Eby G. Friedman

Published in: Integr. (2018)

Keyphrases

chip design
high speed
power consumption
single chip
power dissipation
nm technology
functional verification
building blocks
design methodology
neural network
programmable logic
digital circuits
electrical power
evolvable hardware
cmos technology
design process
low cost
evolutionary algorithm